In order to improve the performance of fuel consumption in automobiles and to purify the exhaust gas from the automobiles, engine control has been conducted electronically and the electronic engine control techniques have been advanced. An igniter is a spark plug controller that feeds electric energy to a spark plug through an ignition coil. An IGBT (insulated gate bipolar transistor) is used for the switching device of an ignition system. The IGBT is advantageous, since the driver circuit configuration for driving the IGBT is simple, the IGBT exhibits excellent protection performances against reverse battery connection and the SOA of the IGBT is wide.
For obtaining high reliability and high performances, a one-chip intelligent IGBT which integrates a control circuit, an overheat detection function and a current control function has been put into market. FIG. 59 is a block circuit diagram of a standard ignition system that uses an IGBT. For the circuit configuration shown in FIG. 59, a self-separation process that exhibits excellent cost performances is employed to integrate an IGBT 101, a control IC 102, a surge protection diode 103, a resistor 104 and a clump diode 105 into one chip. In FIG. 59, an ignition coil 106 and a spark plug 107 are also shown.
FIG. 60 is a cross sectional view showing the integrated structure of IGBT 101 and an NMOS transistor in control IC 102 in FIG. 59. A low-voltage lateral NMOS transistor 110 is formed such that NMOS transistor 110 includes a p−-type well region 118 in the surface portion of an n−-type drift layer 113. The source electrode 125b of low-voltage lateral NMOS transistor 110 is connected electrically to the gate electrode 121a of IGBT 101 and to an input terminal 108 connected to control IC 102 in the ignition system. If a negative input signal is fed to the gate terminal of the intelligent IGBT, the parasitic thyristor shown in FIG. 61 is activated, destroying the intelligent IGBT.
FIG. 61 is a cross sectional view schematically showing the parasitic thyristor associated with low-voltage lateral NMOS transistor 110. The parasitic thyristor is formed by a thyristor connection of a PNP transistor and an NPN transistor. The PNP transistor includes an emitter region formed by a p+-type collector layer 111, a base region formed by an n+-type buffer layer 112 and n−-type drift layer 113, and a collector region formed by p−-type well region 118. The NPN transistor includes an emitter region formed by the n+-type source region 123 of low-voltage lateral NMOS transistor 110, a base region formed by p−-type well region 118, and a collector region formed by n+-type buffer layer 112 and n−-type drift layer 113.
Since the PN diode formed by the n+-type source region 123 and the p−-type well region 118 is forwardly biased when a negative input signal is input to the gate terminal (G) of IGBT 101, the parasitic thyristor is activated. To prevent the parasitic thyristor from functioning, it is necessary to apply a protection network formed by Zener diodes 121 and resistors 122 between input terminal 108 and the gate terminal (G) of IGBT 101 and to connect the protection network to the n+-type source region 123 and the p−-type well region 118 of the low-voltage lateral NMOS transistor 110. For securing a high electrostatic discharge (ESD) withstanding capability for the protection network, it is imperative to set the PN-junction width of the Zener diode 121 to be between several mm and several tens mm, resulting in a wide chip area.
If the intelligent IGBT, which integrates IGBT 101, control IC 102, surge protection diode 103, resistor 104 and clump diode 105 into one chip (cf. FIG. 59), is manufactured by the SOI process, the heat generated in the device will be hardly dissipated, causing troubles. The heat generated in the device is hardly dissipated, since the thermal resistivity of the SiO2 layer buried in the chip is about one hundred times higher than that of silicon. Moreover, since the ESD protection devices manufactured on the SOI is weaker than the protection device manufactured on the bulk wafer, it is not preferable to use the intelligent IGBT manufactured on the SOI wafer for automobiles application. Since the SOI wafer is from 5 to 6 times as expensive as the usual bulk wafer, its wide adoption in consumer application has not yet been achieved.
Types of Insulated-gate power semiconductor devices, which have a structure including an oxide film and such an insulator layer buried locally in the device (partial SOI structure), are known to those skilled in the art (cf. the following Patent Documents 1 and 2). FIG. 62 is a cross sectional view of the semiconductor device equivalent to the semiconductor device disclosed in the Patent Document 1. Referring now to FIG. 62, an oxide film 115 is buried locally between n−-type drift layer 113 and an n-type semiconductor layer 117 in the device surface. The n-type semiconductor layer 117 and n−-type drift layer 113 are in contact with each other in the area, therein oxide film 115 is not present.
A p−-type well region 118 formed locally on oxide film 115 is in contact with n−-type drift layer 113 in the area, therein oxide film 115 is not present. However, p−-type well region 118 is not extended below oxide film 115. Besides, a semiconductor apparatus, which includes a vertical insulated gate power transistor with a semiconductor substrate as one of its constituent elements thereof and a lateral insulated gate power transistor in a SOI structure formed on an insulator film covering the semiconductor substrate, is known to those skilled in the art (cf. the following Patent Document 3).    [Patent Document 1] Published Japanese Translation of PCT International Publication for Patent Application 2001-515662    [Patent Document 2] Publication of Unexamined Japanese Patent Application Hei. 9 (1997)-270513    [Patent Document 3] Publication of Unexamined Japanese Patent Application Hei. 9 (1997)-312398